1. Field of the Invention
The present invention relates to a plasma display panel comprising an energy recovery circuit and a driving method thereof, and more particularly, to a plasma display panel capable of removing a peak voltage of a scan electrode and a driving method thereof.
2. Description of the Background Art
In a general plasma display panel, ultraviolet rays of 147 nm emitted by discharging a He—Xe gas mixture or a Ne—Xe gas mixture excite phosphors. Images of characters or graphics are displayed on the plasma display panel by the excited phosphors.
FIG. 1 shows a structure of a related art plasma display panel.
As shown in FIG. 1, a plasma display panel 30 comprises a scan electrode 12A and a sustain electrode 12B formed on a front substrate 10 and a data electrode 20 formed on a rear substrate 18.
The scan electrode 12A and the sustain electrode 12B each comprise a transparent electrode and a bus electrode. The transparent electrode is formed of indium-tin-oxide (ITO) and the bus electrode is formed of a metal capable of reducing a resistance of the transparent electrode.
An upper dielectric layer 14 and a protective layer 16 are stacked on the front substrate 10 on which the scan electrode 12A and the sustain electrode 12B are formed.
Wall charges generated by a plasma discharge of the plasma display panel 30 are accumulated on the upper dielectric layer 14. The protective layer 16 prevents a damage of the upper dielectric layer 14 caused by sputtering generated by the plasma discharge, and also increases a secondary electron emission coefficient. The protective layer 16 is generally formed of MgO.
A lower dielectric layer 22 and a barrier rib 24 are formed on the rear substrate 18 on which the data electrode 20 is formed. A phosphor layer 26 is coated on the surfaces of the lower dielectric layer 22 and the barrier rib 24.
The data electrode 20 is formed to intersect the scan electrode 12A and the sustain electrode 12B. The barrier rib 24 is formed in parallel with the data electrode 20. The barrier rib 24 prevents the ultraviolet rays and visible light emitted by the plasma discharge from being radiated to adjacent discharge cells.
The ultraviolet rays generated by the plasma discharge excite the phosphor layer 26 to generate any one of red, green or blue light. A He—Xe gas mixture or a Ne—Xe gas mixture is injected into a discharge space of the discharge cell between the front and rear substrates 10 and 18 and the barrier rib 24.
FIG. 2 shows a driving waveform of a related art plasma display panel.
As shown in FIG. 2, the related art plasma display panel is driven by dividing each of a plurality of subfields into a reset period for initializing the whole screen, an address period for selecting cells to be discharged, a sustain period for maintaining discharges of the selected cells, and an erase period for erasing wall charges in the discharged cells.
In the reset period, a rising pulse Ramp-up is simultaneously applied to all scan electrodes Y during a set-up period SU to generate a dark discharge within discharge cells of the whole screen. By the discharge performed during the set-up period SU, positive wall charges are accumulated on address electrodes X and sustain electrodes Z, while negative wall charges are accumulated on the scan electrodes Y.
A falling pulse Ramp-down is applied to the discharge cells during a set-down period SD. The falling pulse Ramp-down which falls from a positive voltage less than a peak voltage of the rising pulse Ramp-up to a ground voltage or a certain negative voltage partially removes wall charges excessively formed in the cells. As a result, wall charges required for performing a stable address discharge uniformly remains in the cells.
In the address period, a scan pulse Sp is sequentially applied to the scan electrodes Y and at the same time, a data pulse Dp is applied to the address electrodes X in synchronous with the scan pulse Sp. A data voltage Vd of the data pulse Dp is commonly 65 V.
While the voltage difference between the scan pulse Sp and the data pulse Dp is added to the wall charges produced during the reset period, the address discharge is generated within the discharge cells to which the data pulse Dp is applied. Wall charges required for a sustain discharge generated by supplying a sustain voltage Vs are formed within the cells selected by the address discharge.
A bias voltage Zdc is supplied to the sustain electrodes Z during the set-down period SD and the address period to decrease the voltage difference between the sustain electrodes Z and the scan electrodes Y. Accordingly, the supply of the bias voltage Zdc prevents misdischarge between the sustain electrodes Z and the scan electrodes Y.
In the sustain period, a sustain pulse SUSp is alternately applied to the scan electrodes Y and the sustain electrodes Z. While the wall voltages within the cells selected by the address discharge are added to the sustain pulse SUSp, a sustain discharge, that is, a display discharge is generated between the scan electrodes Y and the sustain electrodes Z whenever the sustain pulse SUSp is applied.
In the erase period, after completing the sustain discharge, an erase pulse Ramp-ers having a narrow pulse width and a low voltage is supplied to the sustain electrodes Z to remove the wall charges remaining in the cells of the whole screen.
FIG. 3 is a related art energy recovery circuit diagram of the plasma display panel.
As shown in FIG. 3, when the plasma display panel is driven according to the driving waveform of FIG. 2, the sustain pulse SUSp is formed by an energy recovery circuit. When the plasma display panel is normally driven, charges corresponding to 0.5 Vs are charged to a capacitor C of the energy recovery circuit. When a first switch Q1 is turned on in a charged state of the capacitor C, a voltage of the scan electrode Y rises up to a sustain voltage Vs by LC resonance between the plasma display panel and an inductor L. When a second switch Q2 is turned on, a voltage of the scan electrode Y is maintained with the sustain voltage Vs. When a third switch Q3 is turned on, a voltage of the scan electrode Y falls to a ground voltage GND by LC resonance between the plasma display panel and the inductor L. Afterwards, when a fourth switch Q4 is turned on, a voltage of the scan electrode Y is maintained with the ground voltage GND.
FIG. 4 shows a voltage waveform of the scan electrode shown according to an operation of the energy recovery circuit of FIG. 3 when initially driving the plasma display panel.
As shown in FIG. 4, when the plasma display panel is initially driven by the supply of a power supply, charges corresponding to 0.5 Vs are not charged to the capacitor C of the energy recovery circuit. Afterwards, the charges corresponding to 0.5 Vs are charged to the capacitor C by continuously performing turn-on and turn-off operations of the first to fourth switches Q1 to Q4 in order.
In a period indicated by a reference numeral {circle around (1)} of FIG. 4, when the first switch Q1 is turned on in a state that the charges corresponding to 0.5 Vs are not charged to the capacitor C, a voltage of the scan electrode Y rises up to a voltage less than the sustain voltage Vs.
Next, in a period indicated by a reference numeral {circle around (2)} of FIG. 4, when the second switch Q2 is turned on, the sustain voltage Vs is applied to the scan electrode Y. Here, since the voltage difference between the sustain voltage and the voltage of the scan electrode Y is large, a large current flows to the energy recovery circuit. As a result, a peak voltage of the scan electrode Y is generated. When the peak voltage generated in the scan electrode Y is larger than a breakdown voltage of the switches or diodes constituting the energy recovery circuit, problems in normal operations of the switches or the diodes are generated.